Cell scaling is of critical importance to continued improvement of complementary metal-oxide-semiconductor (CMOS) technology. A VFET is a promising device to enable device scaling beyond the 5 nm technology node. To achieve the requisite small SRAM cell, vertical nanowire (VNW) contacts are employed. However, forming vertical cross-couple gate contacts at this scale poses a number of known process and structural challenges.
A need therefore exists for methodology enabling formation of a cross-couple/pull down (PD) transistor/pullup (PU) transistor contact to achieve a small SRAM cell without the known process and structural challenges and the resulting device.